This invention relates to improvements in non-volatile, self restoring memories as referred to and disclosed in my prior copending application, Ser. No. 54,973, filed May 5, 1987, with respect to which the present application is a continuation-in-part.
According to the disclosure in my aforementioned prior copending application, which is incorporated herein by reference, the top electrode plate of the capacitor in each of the cells of a ferroelectric memory array was logically active in controlling capacitor polarization by a controlled supply of high and low voltages thereto. The logic drive circuitry necessary to control the supply of such different voltages to the top electrode plates of the capacitors in the memory cells, renders the associated memory array somewhat costly to manufacture and dimensionally extensive. Further, the voltage plate lines associated with such logic drive circuitry may be a troublesome source of disturbances.
It is therefore an important object of the present invention to provide a memory array of the foregoing type which is capable of being fabricated with greater facility and higher density by solid state chip manufacturing techniques.
A further object in accordance with the foregoing object is to provide a ferroelectric memory array that is less prone to disturbances.